Integrating Reusable Cores from Multiple Sources Is Essential in System-on-a-chip Design. the Authors Present a Hierarchical Methodology for Testing These Cores and the Integrated System

0272-1732/02/$17.00  2002 IEEE The advent of the core-based system-on-a-chip (SOC) and reuse methodologies enables integration of cores from different sources into a single chip. Compared with the traditional multichip system on a board, SOCs offer benefits including higher performance, lower power consumption, smaller size, and so on. Different types of cores are usually incorporated into a single SOC design. These cores can include CPUs, digital signal processors, synchronous RAM, flash memory, analog-to-digital converters, digital-to-analog converters, and phase-locked loops. In addition to these types, some cores are hierarchical compositions, that is, one complex core composed of multiple simple cores. Although the SOC design process is analogous to that for boards, a SOC’s manufacturing test methods are quite different. Board providers have already tested the ICs on the board. Normally, SOC integrators only need to test the board interconnects for manufacturing defects. In SOC design, however, the cores are not yet manufactured and tested. The core integrator is responsible for manufacturing and testing the chip, including the cores. SOC testing includes core internal and external tests, core test knowledge transfer, test access, test integration and optimization, and so on. Testing SOCs is more challenging than testing boards. Recently, researchers have reported results in testing SOCs using architectures compliant with IEEE 1149.1, also known as the Joint Test Action Group (JTAG) standard. One work proposes a systematic solution for accessing embedded JTAG cores hierarchically, using a test access port (TAP) linking module to handle the interaction between the upstream and downstream TAP controllers. Another work reported a hierarchical TAP architecture. This architecture supports test access to embedded JTAG cores with a snoopy TAP. The pin requirement and behavior of this design’s TAP controller is fully compatible with IEEE 1149.1. However, these methods do not handle the test control of IEEE P1500 cores, an important capability because P1500 is more suitable for core-based SOC testing and is getting more and more popular. Another research project uses a central TAP controller consisting of an 1149.1-like TAP finite-state machine and a counter to control P1500 and other cores with a TAP. Another test control mechanism provides a hierarchical test capability for IEEE 1149.1 and P1500 cores, but it requires 10 additional pins to operate the major component—the central test controller—and tests only one core at a time. In all these works, researchers did not consider controlling Jin-Fu Li